A conventional semiconductor package 1 illustrated in FIGS. 7A and 7B includes a package substrate 2 and a semiconductor chip or die 3 located on the substrate. The lower or frontside of the chip carries an integrated circuit which has a plurality of sites or connections for purposes of electrically contacting the integrated circuit to respective contact pads 4 on the package substrate, electronically connecting the chip to the package substrate. More particularly, the die has standoff 5 mounted thereon The standoff are formed of an electrically conductive, high melting temperature material, such as copper. The standoffs are electrically connected to the respective sites or connections of the integrated circuit on the chip. Soldered joints 6 in turn join the die standoffs to the contact pads on the package substrate. The soldered joints are formed in the conventional assembly process wherein the die with standoffs and the substrate with contact pads to which solder has been previously applied, are located in contact with one another and heated together to a temperature higher than the solder melting temperature and allowed to cool-down together. The solder on the contact pads of the substrate is reflowed during this joining process to wet the standoffs and form the soldered joints.
The semiconductor chip in the conventional semiconductor package is typically made of silicon, which has a coefficient of thermal expansion (CTE) of about 2.6-3.3 ppm/° C. (parts per million per ° C.). In the past, the package substrate was generally made of a ceramic material, which has a CTE that is typically below 6 ppm/° C. During heating or cooling of the semiconductor package, including that associated with soldering during assembly of the package, the mismatch of the CTEs of the semiconductor chip and the package substrate was not of a magnitude which caused substantial bending of the semiconductor chip. Nevertheless, this mismatch can still present problems, especially in brittle materials from residual stresses as a result of soldering.
In recent years, there has been a move away from the use of ceramic as a package substrate material to alternative materials, such as plastics or other organic materials, which have lower cost, superior electrical characteristics. A problem with these alternate materials is that they usually have relatively high CTEs, compared to the CTE of the semiconductor chip. Some plastic substrates, for example, have CTEs on the order of 17 ppm/° C. The relatively larger CTE mismatch in packages using the higher CTE package substrate materials can induce adverse effects such as solder fatigue, package and die warpage, die cracking, etc. These problems can occur at the time of joining the chip to the substrate or subsequently during the operating life of the package.
Numerous proposals have been made to reduce the problems arising from CTE mismatch in package materials. For example, U.S. Pat. No. 5,369,551 proposes a surface mount stress relief interface system and method wherein a compliant interface device is connected to both the substrate and chip for obviating CTE mismatch. In Assignee's U.S. Pat. No. 5,889,652, a bond portion of the substrate is separated from a contact portion of the substrate by a flexible portion to allow relative movement to minimize the stresses on the solder joints.
U.S. Pat. No. 5,931,311 discloses a standoff controlled interconnection for use in a soldering process to reduce solder joint plastic deformation caused by CTE mismatch. The patentees explain that the larger the standoff, the less plastic deformation that occurs, thus leading to a longer component/interconnection durability and cycles life.
Another approach taken to reduce the effect of CTE mismatch on the life of the semiconductor package involves reinforcement of the chip against warpage. For example, the use of a protective layer on the backside of the die is suggested in Assignee's U.S. Pat. No. 5,936,304. In a further example, the semiconductor chip is provided with beveled edges which, together with an epoxy located thereon, reduce stresses on the chip when the package is heated, as disclosed in Assignee's U.S. Pat. No. 6,049,124.
The problems related to CTE mismatch induced effects on semiconductor packages have become more pronounced as dies have become larger because of the increased distance from the center of the die to sites at which the die and substrate are joined to one another. There is a need for an improved method of joining CTE mismatched materials and an electronic assembly/semiconductor package made thereby, wherein CTE mismatch induced effects such as solder fatigue, package and die warpage, die cracking, etc., are reduced or minimized.